Microchip Announces DRAM Controller For OpenCAPI Memory Interface

Microchip’s subsidiary Microsemi is entering a new market with the introduction of the SMC 1000 8x25G Serial Memory Controller. This is a DDR4 DRAM controller that connects to host processors using the OpenCAPI-derived Open Memory Interface (OMI), a high-speed differential serial link running at 25Gbps per lane. The purpose is to enable servers to scale to much higher memory capacities by attaching DRAM through serial links with much lower pin counts than traditional parallel DDR interfaces.

OpenCAPI is one of several competing high-speed interconnect standards that seek to go beyond the performance and feature set of PCI Express. The first two CAPI standards were built atop PCIe 3.0 and 4.0 and offered a lower-latency, cache-coherent protocol. Version 3 gained the Open- prefix by moving control of the spec from IBM to a new consortium, and OpenCAPI 3.0 abandons its PCIe underpinnings in favor of a new 25Gbps link. A subset of OpenCAPI 3.1 has been dubbed Open Memory Interface, and provides a media-agnostic but low-latency protocol for accessing memory. There’s open IP available for implementing the host or target side of this interface, and a growing ecosystem of commercial tools for design verification.

The Microchip SMC 1000 8x25G unsurprisingly uses an 8-lane Open Memory Interface connection to the host, and on the downstream side it has a single-channel DDR4-3200 controller with ECC and support for four ranks of memory. The SMC 1000 at heart is a SERDES with a few extra features, allowing a CPU to use an 84-pin connection in place of a 288-pin DIMM interface, without sacrificing bandwidth and only incurring an extra 4ns of latency compared to LRDIMMs attached to an on-CPU memory controller. The chip itself is a 17×17 mm package with typical power consumption below 1.7W, and it supports dynamically dropping down to four or two lanes on the OMI link to save power when the full 25GB/s isn’t needed.

In principle, the DRAM interface of the SMC 1000 could fan out to traditional DIMM slots, but the preferred way to use the chip will be to put the controller and a fixed amount of DRAM together onto a module called a Differential DIMM. These DDIMMs will use the same SFF-TA-1002 connector as EDSFF/Ruler SSDs, and the modules will be 85mm long compared to 133mm LRDIMMs. Both 1U and 2U height DDIMM form factors are in the process of being standardized. Microchip already has Samsung, Micron and SMART Modular on board to manufacture DDIMMs using the SMC 1000 controller, with initial capacities ranging from 16GB to 256GB per module.

On the host side, the first platforms to support Open Memory Interface will be POWER9 processors from IBM, and they are expected to announce more details later this month at their OpenPOWER Summit. From IBM’s perspective, supporting Open Memory Interface allows them to include more memory channels on the same size die, and provides a forward-compatible upgrade path to DDR5 and NVDIMMs or other memory technologies since the details of those interfaces are now handled on the DDIMM instead of on the CPU.

Microchip will be showing off the SMC 1000 8x25G at Flash Memory Summit this week, and will be giving a keynote presentation Wednesday morning.